SiC MOSFETs (metal-oxide-semiconductor field effect transistors) suffer from low electron mobility at the SiC—SiO2 interface which is due to carbon-related interface defects resulting from thermal oxidation of SiC. Electron scattering at such charged point defects at the SiC—SiO2 interface results in the mobility (e.g. 5-50 cm2/Vs) typically only being a fraction of the bulk mobility (e.g. 800 cm2/Vs). Also, a 4° off-axis tilt is typically present along the <11-20> crystal direction (parallel to the flat wafer). The 4° off-axis tilt is a consequence of the crystal growth and cannot be avoided. Because of this tilt the wafer surface does not perfectly coincide with the (0001) crystal c-plane, causing a rough surface and steps along the <11-20> direction. The off-axis cut is not only a problem for planar technologies such as lateral MOSFETs and DMOSFETs which have a MOS channel at the wafer surface, but also for trench MOSFET technologies. A vertically etched trench with arbitrary orientation in general has two side walls with different roughness, performance and reliability, making it difficult to use both side walls of the trench as a high-mobility MOS channel.
Another problem associated with SiC MOSFETs is that the high breakdown field of the SiC material (typically 2 MV/cm) can usually only be used if the gate dielectric is properly protected. The electric field in the gate dielectric may increase by a factor of 2.5 if the electric field in the SiC approaches the avalanche break down field of SiC (2.2 MV/cm). Accordingly, SiC MOSFETs are typically designed in a way so that the electric field in the gate dielectric is limited under all operating conditions. This is typically done by deep p-type implants which form a JFET (junction FET)-like structure below the gate trench. However, the cell design also impacts on-resistance (Ron×A or Ron). To achieve a low on-resistance (Ron×A or Ron) and good shielding of the gate dielectric, the cell design should maximize the active channel area while providing sufficient protection for the gate dielectric.
Thus, there is a need for a SiC-based power semiconductor device having a cell design which maximizes the active channel area while providing sufficient protection for the gate dielectric.